In recent years, flat panel display devices have been developed for use in many electronic applications including notebook computers. One such device, an active matrix liquid crystal display, has been used frequently. However, the liquid crystal display device has inherent limitations that render it unsuitable for many applications. For instance, liquid crystal displays have fabrication limitations such as a slow deposition process of amorphous silicon on glass, high manufacturing complexity and low yield. The displays require a power-hungry fluorescent backlight while most of the light is wasted. A liquid crystal display image is also difficult to see in bright sunlight or at extreme viewing angles which present a major concern in many applications.
A more recently developed device of a field emission display (FED) overcomes some of these limitations and provides significant benefits over the liquid crystal display devices. For instance, the FEDs have higher contrast ratio, larger viewing angle, higher maximum brightness, lower power consumption and a wider operating temperature range when compared to a typical thin film transistor liquid crystal display device.
Unlike the liquid crystal displays, field emission displays (FEDs) produce their own light using colored phosphors. The FEDs do not require complicated, power-consuming backlights and filters and almost all the light generated by an FED is visible to the user. The FEDs do not require large arrays of thin-film transistors. A major source of yield problems for active matrix liquid crystal displays is therefore eliminated.
In a FED, electrons are emitted from a cathode and impinge on phosphors on the back of a transparent face plate to produce an image. It is known that such a cathodoluminescent process is one of the most efficient ways for generating light. Unlike a conventional CRT, each pixel in an FED has its own electron source, typically an array of emitting microtips. The voltage difference between the cathode and the gate extracts electrons from the cathode and accelerates them towards the phosphors. The emission current and thus the display brightness, is strongly dependent on the work function of the emitting material. The cleanliness and uniformity of the emitter source material are therefore essential.
Most FEDs are evacuated to low pressures, i.e., 10.sup.-7 torr, to provide a long mean free path for emitted electrons and to prevent contamination and deterioration of the tips. Display resolution is improved by using a focus grid to collimate the electrons drawn from the microtips.
The first field emission cathodes developed for a display device used a metal microtip emitter of molybdenum. In such a device, a silicon wafer is first oxidized to produce a thick SiO.sub.2 layer and then a metallic gate layer is deposited on top of the oxide. The gate layer is then patterned to form gate holes. Etching the SiO.sub.2 underneath the holes undercuts the gate and creates a well. A sacrificial layer such as Ni is deposited to prevent deposition of nickel into the emitter well. Molybdenum is then deposited at normal incidence such that a cone with a sharp point grows inside the cavity until the hole closes above it. An emitter cone is left when the sacrificial layer is removed.
In another FED device, silicon microtip emitters are produced by first thermal oxidation of silicon and followed by patterning of the oxide and selective etching to form silicon tips. Further oxidation or etching protects the silicon and sharpens the point to provide a sacrificial layer.
In an alternative design, the microtips are added onto a substrate of desired materials such as glass, which is an ideal substrate material for large area flat panel display. The microtips can be made of conducting materials such as metals or doped semiconductors. In such a FED device, an interlayer with controlled conductivity between the cathode and the microtips is highly desirable. Proper engineering of the resistivity of the interlayer enables the device to operate in a stable and controllable fashion. The resistivity of the interlayer is in the order between an insulator and a conductor, while the actual desired value depends on the specifics of the device design.
Chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) are processes widely used in the manufacture of semiconductor devices for depositing layers of materials on various substrates. In a conventional PECVD process, a substrate is placed in a vacuum deposition chamber equipped with a pair of parallel plate electrodes. The substrate is generally mounted on a susceptor which is also the lower electrode. A reactant gas flows into the deposition chamber through a gas inlet manifold which also serves as the upper electrode. A radio frequency (RF) voltage is applied between the two electrodes which generates an RF power sufficient to cause a plasma to be formed in the reactant gas. The plasma causes the reactant gas to decompose and deposit a layer of the desired material on the surface of the substrate body. Additional layers of other electronic materials can be deposited on the first layer by flowing into the deposition chamber a reactant gas containing the material of the additional layer to be deposited. Each reactant gas is subjected to a plasma which results in the deposition of a layer of the desired material.
In the fabrication of a field emission display device, it is desirable to deposit an amorphous silicon based film that has electrical conductivity in an intermediate range between that of intrinsic amorphous silicon and n.sup.+ doped amorphous silicon. The conductivity of the n.sup.+ doped amorphous silicon is controlled by adjusting the amount of phosphorus atoms contained in the film. Even though it is possible, in principle, to produce an intermediate conductivity film by adding very small amounts of phosphorus atoms, it is a very difficult task, i.e. requires specially premixed PH.sub.3 /H.sub.2 to precisely control the amounts of the phosphorus atoms.
Since field emitting display devices use very thick layers, it becomes necessary to deposit low stress films to prevent warping of the glass and peeling of the films. The standard process for depositing amorphous silicon produces films that are highly compressive, especially when deposited at high deposition rates.
It is therefore an object of the present invention to provide a method of depositing amorphous silicon based films that have controlled conductivity in a chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process that does not have the shortcomings of the prior art methods.
It is another object of the present invention to provide a method of depositing amorphous silicon based films that have controlled conductivity and low stress in a chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process by incorporating simple process control steps.
It is still another object of the present invention to provide a method of depositing amorphous silicon based films that have controlled conductivity and low stress in a chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process by using a reactant gas mixture containing PH.sub.3 and NH.sub.3.
It is yet another object of the present invention to provide a method of depositing amorphous silicon based films that have controlled conductivity and low stress in a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process by controlling the flow rates of the reactant gases in the reaction chamber.